Abstracting out the electrical details, I made a map to simulate digital design, which in its essence is logic circuits like "x AND y = z", but becomes immensely more interesting with sequential circuits, where memory is maintained. Thus, sequential circuit design was of core importance when making this map, and sequential circuits are possible.
Kind of lazy to explain the specifics without a demand, but a lot of it should be self evident if you have knowledge of digital design. Here is an implementation of an S-R latch, clearly showing output that is based on state other than its current input.
The beauty of this doesn't lie in the functional result itself, but in the fact that the entire circuit is only composed of:
1) SOURCE (hydralisk) - provides a signal
2) LINE (zergling) - conducts the signal
3) GATE (defiler) - restricts or conducts a signal (there is a distinction between UP and DOWN gates, for unburrowed and burrowed respectively. The CMOS analogue to these would be NMOS and PMOS transistors).
And for convenience,
4) JOINT (infested terran) - basically a LINE that you can move around or burrow without it getting Given away.
I currently haven't tried to go beyond a simple Latch circuit, and I don't know if this map works for circuits more complex involving multiple latches/flip-flops, as there is no inherent synchronicity to any system, as there is no clock. I'll find that out later, but for now I'm deciding to release what I've made so far.
http://www.staredit.net/?file=2950
Post has been edited 1 time(s), last time on Apr 2 2014, 9:41 pm by yoonkwun.
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